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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of devi ce specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. in addition, generalplus products are not authorized for use as critical components in life support devices/ systems or aviatio n devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus. oct. 01, 2013 version 1.4 g g p p c c e e 0 0 4 4 0 0 a a 1 1 6 6 - - b b i i t t s s o o u u n n d d c c o o n n t t r r o o l l l l e e r r w w i i t t h h 2 2 4 4 k k x x 1 1 6 6 r r o o m m
GPCE040A ? generalplus technology inc. proprietary & confidential 2 oct 01, 2013 version: 1.4 table of contents page 1. general description .................................................................................................................... ...................................................... 4 2. block diagram ........................................................................................................................ .............................................................. 4 3. features....................................................................................................................... ........................................................................... 4 4. application field.......................................................................................................................... ........................................................ 4 5. signal descriptions................................................................................................................... ......................................................... 5 5.1. pad a ssignment ............................................................................................................................... .................................................. 6 6. functional descriptions................................................................................................................... ............................................... 7 6.1. cpu ............................................................................................................................ ......................................................................... 7 6.2. m emory ............................................................................................................................... ................................................................ 7 6.2.1. sram........................................................................................................................... ............................................................. 7 6.2.2. rom............................................................................................................................ .............................................................. 7 6.3. pll, c lock , p ower m ode ............................................................................................................................... .................................... 7 6.3.1. pll (phase lock loop).......................................................................................................... ................................................... 7 6.4. s tandby m ode ............................................................................................................................... ...................................................... 7 6.5. l ow v oltage d etection and l ow v oltage r eset ............................................................................................................................. 8 6.5.1. low voltage detection (lvd) .................................................................................................... ................................................. 8 6.5.2. low voltage reset .............................................................................................................. ........................................................ 8 6.6. i nterrupt ............................................................................................................................... ............................................................. 8 6.7. i/o ............................................................................................................................ ............................................................................ 8 6.8. t imer /c ounter ............................................................................................................................... .................................................... 9 6.8.1. timebase ....................................................................................................................... ......................................................... 10 6.9. s leep , w akeup and w atchdog ............................................................................................................................... .......................... 10 6.9.1. wakeup and sleep ............................................................................................................... ................................................... 10 6.9.2. watchdog ....................................................................................................................... ......................................................... 10 6.10. adc (a nalog to d igital c onverter ) / dac ............................................................................................................................ ........ 10 6.11. s erial interface i/o (sio).......................................................................................................................... .......................................11 6.12. uart ........................................................................................................................... .......................................................................11 6.13. a udio a lgorithm ............................................................................................................................... .................................................11 6.14. b onding o ption s ummary ............................................................................................................................... ..................................11 6.14.1. watchdog function.............................................................................................................. .................................................11 7. electrical specifications ................................................................................................................. ............................................ 12 7.1. a bsolute m aximum r atings ............................................................................................................................... .............................. 12 7.2. dc c haracteristics (vdd = 3.3v, vdd io = 5.5v (p ort a & b), t a = 25 ) ....................................................................................... 12 7.3. dc c haracteristics (vdd = 3.3v, vdd io = 3.3v (p ort a & b), t a = 25 ) ....................................................................................... 12 7.4. dc c haracteristics (vdd = 2.7v, vdd io = 2.7v (p ort a & b) , t a = 25 ) ...................................................................................... 13 7.5. dc c haracteristics (vdd = 2.4v, vdd io = 2.4v (p ort a & b) ,t a = 25 ) ....................................................................................... 13 7.6. adc c haracteristics (vdd = 3.3v, t a = 25 ) .............................................................................................................................. .. 14 7.7. dac c haracteristics (t a = 25 ) .............................................................................................................................. ...................... 14 7.8. p ull h igh r esister and vdd io ............................................................................................................................... .......................... 15 7.9. i/o o utput h igh c urrent i oh and v oh ............................................................................................................................... ............... 15 7.10. p ull l ow r esister and vdd io ............................................................................................................................... ........................... 15 7.11. i/o o utput l ow c urrent i ol and v ol ............................................................................................................................... ................ 15
GPCE040A ? generalplus technology inc. proprietary & confidential 3 oct 01, 2013 version: 1.4 8. application circuits ....................................................................................................................... .................................................. 16 8.1. a pplication c ircuit - (1) ............................................................................................................................ ....................................... 16 8.2. a pplication c ircuit - (2) ............................................................................................................................ ....................................... 17 8.3. a pplication c ircuit - (3) ............................................................................................................................ ....................................... 18 8.4. a pplication c ircuit - (4) ............................................................................................................................ ....................................... 19 8.5. a pplication c ircuit - (5) ............................................................................................................................ ....................................... 20 8.6. a pplication c ircuit - (6) ............................................................................................................................ ....................................... 21 9. package/pad locations ...................................................................................................................... ............................................. 22 9.1. o rdering i nformation ............................................................................................................................... ...................................... 22 9.2. p ackage information ............................................................................................................................... ........................................ 22 9.2.1. lqfp 80........................................................................................................................ .......................................................... 22 10. disclaimer..................................................................................................................... ........................................................................ 25 11. revision history ........................................................................................................................ ......................................................... 26
GPCE040A ? generalplus technology inc. proprietary & confidential 4 oct 01, 2013 version: 1.4 16-bit sound controller with 24k x 16 rom 1. general description the GPCE040A, a 16-bit architecture product, carries the newest 16-bit microprocessor, ?nsp? (pronounced as micro-n-sp), developed by sunplus technology. this high processing speed assures the ?nsp? is capable of handling complex digital signal processes easily and rapidly. therefore, the GPCE040A is applicable to the areas of digital sound process and voice recognition. the operating voltage of 2.4v through 3.6v and speed of 0.32mhz through 49.152mhz yield the GPCE040A to be easily used in varieties of applications. the memory capacity includes 24k-word fast-speed rom plus a 2k-word working sram. other features include 32 programmable multi-functional i/os, two 16-bit timers/counters, 32768hz real time clock, low voltage reset/detection, eight channels 10-bit adc (one channel built-in mic amplifier with auto gain controller), 10-bit dac output and many others. 2. block diagram 16-bit 16-bit timer/counter x 2 cpu clock 32 pin general i/o port lvd/lvr watchdog rtc rom ram u'nsp timerbase int control x32i x32o ioa15 - 0 iob15 - 0 vcoin controller uart pll iob7 (rx) iob10 (tx) aud1 aud2 10-bit a/d & agc sio iob1 (sda) iob0 (sck) sleep reset 10-bit dac1 output 10-bit dac2 output vmic vextref vadref agc micout micp opi micn fast-speed 3. features ? 16-bit ?nsp? microprocessor ? cpu clock: 0.32mhz - 49.152mhz ? operating voltage: 3.0v - 3.6v @cpu clock = 49.152mhz operating voltage: 2.4v - 3.6v @cpu clock <=40.96mhz ? io porta & b operating voltage: 2.4v - 5.5v ? 24k-word fast-speed rom ? 2k-word working sram ? software-based audio processing ? crystal resonator ? standby mode (clock stop mode) for power savings, max. 2.0 a @ vdd = 3.6v ? two 16-bit timers/counters ? two 10-bit dac outputs ? 32 general i/os (bit programmable) ? 14 int sources with two priority levels ? key wakeup function (ioa0 - 7) ? pll feature for system clock ? 32768hz real time clock (rtc) ? eight channels 10-bit ad converter ? adc external top reference voltage ? 2.0v voltage regulator output, 5ma of driving capability ? serial interface i/o (sio) ? built-in microphone amplifier and agc function ? uart receiver and transmitter (full duplex) ? low voltage reset and low voltage detection ? watchdog enable (bonding option) 4. application field ? voice recognition products ? intelligent interactive talking toys ? advanced educational toys ? kids learning products ? kids storybook ? general speech synthesizer ? long duration audio products ? recording / playback products
GPCE040A ? generalplus technology inc. proprietary & confidential 5 oct 01, 2013 version: 1.4 5. signal descriptions mnemonic pin no. type description ioa [15:8] ioa [7:0] 46 - 39 34 - 27 i/o i/o ioa [15:8]: bi-directional i/o ports. ioa [7:0] can be software programmed to wakeup i/o pins. ioa [6:0] can be optioned as adc line-in input. iob [15:11] iob 10 iob 9 iob 8 iob 7 iob 6 iob 5 iob 4 iob 3 iob 2 iob 1 iob 0 50 - 54 57 58 59 60 61 62 63 64 65 66 67 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o iob [15:11]: bi-directional i/o ports. iob10 can also be selected as uart transmitter (tx). iob9 can also be multi-duty cycle output of timerb (bpwmo). iob8 can also be multi-duty cycle output of timera (apwmo). iob7 can also be selected as uart receiver (rx). iob6 is a bi-directional i/o ports. iob5 can also be selected as feedback signal with ext2. iob4 can also be selected as feedback signal with ext1. iob3 can also be selected as an external in terrupt input pin (ext2)(negative-edge triggered). iob2 can also be selected as an external in terrupt input pin (ext1)(negative-edge triggered). iob1 can also be selected as a serial interface data.(sda). iob0 can also be selected as a serial interface clock (sck). dac1 12 o audio dac1 output. dac2 13 o audio dac2 output. x32i 2 i oscillator crystal input. x32o 1 o oscillator crystal output. vcoin 70 i rc filter connection for pll. agc 16 i agc control pin. micn 19 i microphone differential input (negative). micp 21 i microphone differential input (positive). v2vref 14 o 2.0v output voltage, 5.0ma of driving capability (can be used as external adc line_in top reference voltage). micout 18 o microphone 1 st amplifier output. opi 17 i microphone 2 nd amplifier input. vextref 23 i adc line_in top external reference voltage input pin. vmic 25 o microphone power supply. vadref 22 o ad reference voltage (generated by internal ad converter). vdd 5, 69 i positive supply for logic. vss 8, 10, 26, 71 i ground reference for logic and i/o pins. vddio 37, 38, 56 i positive supply for i/o pins. vssio 35, 36, 48 i ground reference for i/o pins. avdd 24 i positive supply for analog circuit including adc, dac and 2.0v regulator. avss 15 i ground reference for analog circui t including adc, dac and 2.0v regulator. reset 68 i an active low reset to the chip. sleep 49 o sleep mode (active high). test 3 i connected to high for test mode, normally connected to gnd (test m ode disabled) or unconnected. n/c 7, 9, 11, 20, 47, 55 i not used. n/c 4 i do not bonding and connect this pin, if user binding this pin, ic will not work. wdgopt* 6 i bonded for watchdog disabled, unbonded for watchdog enabled. note*: wdgopt is the watchdog option pin, selected by bonding option. remain wdgopt unbonded to enable the watchdog. in contrast, bonding this pad will disable watchdog. the reason of placing wdtopt adjacent to vdd is to facilitate connection between vdd and wdgopt when disabling watchdog is necessary. the layout of wdogpt option pin is drawn in the right. vdd wdgopt
GPCE040A ? generalplus technology inc. proprietary & confidential 6 oct 01, 2013 version: 1.4 5.1. pad assignment ( 0 , 0 ) 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 vddio iob10 iob9 iob8 iob7 iob6 iob5 iob4 iob3 iob2 iob1 iob0 reset vdd vcoin vss 1 2 3 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 22 23 24 25 26 27 28 29 30 31 32 33 34 x32o x32i test vdd n/c vss n/c vss n/c dac1 dac2 v2vref avss agc opi micout micn n/c micp vadref vextref avdd vmic vss ioa0 ioa1 ioa2 ioa3 ioa4 ioa5 ioa6 ioa7 vssio vssio vddio 35 36 37 38 39 vddio ioa8 ioa10 ioa9 ioa12 ioa11 ioa14 ioa13 n/c ioa15 sleep vssio iob14 iob15 iob12 iob13 iob11 4 6 55 n/c n/c wdgopt this ic substrate should be connected to vss note1: to ensure the ic functions properly, please bond all of vdd and vss pins. note2: the 0.1 f capacitor between vdd and vss should be placed to ic as closed as possible
GPCE040A ? generalplus technology inc. proprietary & confidential 7 oct 01, 2013 version: 1.4 6. functional descriptions 6.1. cpu the GPCE040A is equipped with a 16-bit ?nsp?, the newest 16-bit microprocessor by sunplus and pronounced as micro-n-sp. eight registers are involved in ?nsp?: r1 - r4 (general-purpose registers), pc (program counter), sp (stack pointer), base pointer (bp) and sr (segment register). the interrupts include three fiqs (fast interrupt request) and eight irqs (interrupt request), plus one software-interrupt, break. moreover, a high performance hardware multiplier with the capability of fir filter is also built in to reduce the software multiplication loading. 6.2. memory 6.2.1. sram the amount of sram is 2k-word (including stack), ranged from $0000 through $07ff with access speed of two cpu clock cycles. fosc/n n:1,2,4,8,16,32,64 b2 b1 b0 of p_systemclock(w )($7013h) cpu clock frequency selection cpu clock 32768hz x'tal b7,b6,b5 of p_systemclock(w )($7013h) system clock frequency selection (default : fosc/8) phase lock loop (pll) system clock generator pll out fosc b7 b6 b5 24.576mhz(default) 20.48mhz 32.768mhz 40.96mhz 49.152mhz 6.2.2. rom the GPCE040A provides a 24k-word fast-speed rom with access speed of two cpu clock cycles. 6.3. pll, clock, power mode 6.3.1. pll (phase lock loop) the purpose of pll is to pr ovide a base frequency (32768hz) and to pump the frequency from 20.48mhz to 49.152mhz for system clock (f osc ). the default pll frequency is 24.576mhz. 6.3.1.1. system clock basically, the system clock is provided by pll and programmed by the port_systemclock (w) to determine the frequency of clock for system. the default system clock f osc = 24.576mhz and cpu clock is fosc/8 if not specified. the initial cpu clock is fosc/8 after system wakes up and to be adjusted to desired cpu clock by programming the port_systemclock (w). 6.3.1.2. 32768hz rtc the real time clock (rtc) is normally used in watch, clock or other time related products. a 2hz-rtc (1/2 second) function is loaded in GPCE040A. the rtc counts the timing as well as to wake cpu up whenever rtc occurs. since the rtc is generated in every 0.5 seconds, time can be traced by the numbers of rtc occurrence. in addition, GPCE040A supports 32768hz oscillator in normal mode and auto-power-saving mode. in normal mode, 32768hz osc always runs at the highest power consumption. in auto-power-saving mode, however, it runs in normal mode for the first 7.5 seconds and changes back to power-saving mode automatically to save powers. 6.4. standby mode the GPCE040A also offers a standby mode for low power application needs. to enter standby mode, the desired key wakeup port(ioa[7:0]) must be configured to input first. and read the port_ioa_latch(r) to latch the ioa state before entering the standby mode. also remember to enable the corresponding interrupt source(s) for wakeup. after that, stop the cpu clock by writing the stop clock register (b0~b2 of port_systemclock (w)) to enter standby mode. in such mode, sram and i/os remain in the previous states till cpu being awoken. the wakeup sources in GPCE040A include port ioa7 - 0 and irq1 - irq6. after GPCE040A is awoken, the cpu will continue to execute the program. programme r can also enable or disable the 32768hz osc when cpu is in standby mode.
GPCE040A ? generalplus technology inc. proprietary & confidential 8 oct 01, 2013 version: 1.4 6.5. low voltage detection and low voltage reset 6.5.1. low voltage detection (lvd) the low voltage detection (lvd) reports the circumstance of present voltage. there are three lvd levels to be selected: 2.5v, 2.9v, and 3.3v. these levels can be programmed via port_lvd_ctrl (w). as an exam ple, suppose lvd is given to 2.9v. when the voltage drops below 2.9v, the b15 of port_lvd_ctrl is read as high. in such state, program can be designed to react to this condition. 6.5.2. low voltage reset in addition to the lvd, the GPCE040A has another important function, low voltage reset (lvr). with the lvr function, a reset signal is generated to reset system when the operating voltage drops below 2.3v for 10 consecutive cpu clock cycles. without lvr, the cpu becomes unstable and malfunctions when the operating voltage drops below 2.3v. the lvr will reset all functions to the initial operational (stable) states when the voltage drops below 2.3v. a lvr timing diagram is given as follows: 2.3v vdd f cpu tvdd tw tw=f cpu x 10 cycle tvdd > tw treset reset treset = f cpu x512 cycle 6.6. interrupt the GPCE040A has 14 interrupt sources, grouped into two types, fiq (fast interrupt request) and irq (interrupt request). the priority of fiq is higher than irq. fiq is the high-priority interrupt while irq is the low-priority one. an irq can be interrupted by a fiq, but not by another irq. a fiq cannot be interrupted by any other interrupt sources. interrupt source interrupt name priority fosc/1024 fiq_pwm/irq0_pwm high(fiq) timer a fiq_tma/ irq1_tma high(fiq) timer b fiq_tmb/ irq2_tmb high(fiq) interrupt source interrupt name priority ext2 irq3_ext2 low ext1 irq3_ext1 low key change wakeup irq3_key low 4096hz irq4_4khz low 2048hz irq4_2khz low 1024hz irq4_1khz low 4hz irq5_4hz low 2hz irq5_2hz low time-base 1 irq6_tmb1 low time-base 2 irq6_tmb2 low uart (txrdy or rxrdy) uart irq low 6.7. i/o two i/o ports are built in GPCE040A, porta and portb. the porta is an ordinary i/o with programmable wakeup capability. in addition to the regular io functi on, the portb can also perform some special functions in cert ain pins. suppose operating voltage is running at 3.6v (vdd) and vddio (power for i/o) operates from 3.6v (vdd) to 5.5v. in such condition, the i/o pad is capable of operating from 0v through vddio. the following diagram is an i/o schematic. register control logic pull high pull low pin pad buffer(r) data(r) port_data(w) port_buffer(w) port_dir(r/w) port_attr(r/w) although data can be written into the same register through port_data and port_buffer, they can be read from different places, buffer (r) and data (r). the ioa [7:0] is the key wakeup port. to activate key wakeup functi on, latch data on port_ioa_latch and enable the key wakeup function. wakeup is triggered when the porta state is different from at the time latched. in addition to an ordinary i/o port, portb carries some special functions. a summary of portb special functions is listed as follows:
GPCE040A ? generalplus technology inc. proprietary & confidential 9 oct 01, 2013 version: 1.4 special function in portb portb special function function description note iob0 sck serial interface clock refer to see sio section iob1 sda serial interface data refer to see sio section ext1 external interrupt source 1(negativ e-edge triggered) iob2 set as input mode iob2 feedback output1 works with iob4 by adding a rc circuit between them to get an osc to ext1 interrupt iob2 set as inverted output ext2 external interrupt source 2(negativ e-edge triggered) iob3 set as input mode iob3 feedback output2 works with iob5 by adding a rc circuit between them to get an osc to ext2 interrupt iob3 set as inverted output iob4 feedback input1 - - iob5 feedback input2 - - iob7 rx uart receiver refer to see uart section iob8 apwmo timera pwm output refer to timer/counter section iob9 bpwmo timerb pwm output refer to timer/counter section iob10 tx uart transmitter refer to uart section default state: pull low pwm: pulse width modulation refer to the above table, the configuration of iob2, iob3, iob4, and iob5 involves feedback function in which an osc frequency can be obtained from ext1 (ext2) by simply adding a rc circuit between iob2 (iob3) and iob4 (iob5). 6.8. timer/counter the GPCE040A provides two 16-bit timers/counters, timera and timerb. the timera is called a universal counter. timerb is a general-purpose counter. the clock source of timera comes from the combination of clock s ource a and clock source b. in timerb, the clock source is given from source c. when timer overflows, an int signal is sent to cpu to generate a time-out signal. clock of source a clock of source b clock of source c fosc/2 2048hz fosc/2 fosc/256 1024hz fosc/256 32768hz 256hz 32768hz 8192hz tmb1 8192hz 4096hz 4hz 4096hz 1 2hz 1 0 1 0 ext1 ext2 ext1 initially, write a value of n into a timer and select a desired clock source, timer will start counting from n, n+1, n+2,... through ffff. an int (timera/timerb) signal is generated at the next clock after reaching ?ffff? and the int signal is transmitted to int controller for further processing. at the same time, n will be reloaded into timer and start all over again. the clock source a is a high frequency source and clock source b is a low frequency source. the combination of clock source a and b provides a variety of speeds to timera. a ?1? represents pass signal and not gating. in contrast, ?0? indicates deactivating timer. the ext1 and ext2 are the external clock sources. moreover, counter can generate time-out signal for input clock sour ce to a four bits (16 levels) pwm pulse width counter. a variety of clock duration can be generated and exported from iob8 (apwmo) and iob9 (bpwmo). the following example is a 3/16-duration cycle. the apwmo waveform is made by selecting a pulse width through port_timera_ctrl (w) [9:6]. as a result, each 16 cycles will generate a pulse width defined in control port. these pwm signals can be applied for controlli ng the speed of motor or other devices.
GPCE040A ? generalplus technology inc. proprietary & confidential 10 oct 01, 2013 version: 1.4 tapwmo tduty apwmo timera_timeout generally speaking, the clock source a and c are fast clock sources and source b comes from rtc system (32768hz). therefore, clock source b can be utilized as a precise counter for time counting, e.g., the 2hz cl ock can be used for real time counting. 6.8.1. timebase timebase, generated by 32768hz, is a combination of frequency selections. the outputs of timebase block are named to tmb1 and tmb2. tmb1 is frequency for timera (clock source b). the tmb1 and tmb2 are the sources for interrupt (irq6). furthermore, timebases generates additional 2hz to 4096hz interrupt sources (irq4 and irq5) for real-time-clock (rtc). tmb2 tmb1 128hz 8hz 256hz 16hz 512hz 32hz 1024hz 64hz default: 128hz default: 8hz 6.9. sleep, wakeup and watchdog 6.9.1. wakeup and sleep 1). sleep: after power-on reset, ic starts running until a sleep command occurs. when a sleep command is accepted, ic will turn the system clock (pll) off. after all, it enters sleep mode. 2). wakeup: cpu waking up from sleep mode requires a wakeup signal to turn the system clock (pll) on. the irq signal makes cpu to complete the wakeup process and initialization. the key wakeup and interrupt sources (irq1 - irq6) can be used for wakeup sources. 6.9.2. watchdog the purpose of watchdog is to monitor if the system operates normally. within a certain period, watchdog must be cleared. if watchdog is not cleared, cpu assumes the program has been running in an abnormal condition. as a result, the cpu will reset the system to the initial state and start running the program all over again. the watchdog functi on can be removed by bonding option. in GPCE040A, the clear period is 0.75 seconds. if watchdog is cleared within each 0.75 seconds, the system will not be reset. to clear watchdog, simply write ?xxxx xxxx xxxx xx01b? to port_watchdog_clear(w). the content written to port_watchdog_clear (w) for watchdog clearance must be exactly the same as the one illustrated above (xxxx xxxx xxxx xx01b). other values given to the port_watchdog_clear (w) for watchdog clearance may end up with system reset. the watchdog function remains enabled during standby mode if the 32768hz is turned on. 6.10. adc (analog to digital converter) / dac the GPCE040A has eight channels 10 -bit adc (analog to digital converter). the function of an a dc is to convert analog signal to digital signal, e.g. a voltage level into a digital word. the eight channels of adc can be seven channels of line-in from ioa [6:0] or one channel microphone (mic) input through amplifier and agc controller. the mic amplifier circuit is capable of reducing common mode noise by transmitting signals through differential mic inputs (micn, micp). moreover, an external resistor can be applied to adjust microphone gain and time of agc operating. the ad needs to select source of line-in before conversion. the adc is able to choose the exte rnal or internal (=avdd) top reference voltage. if constant voltage source is unavailable, GPCE040A offers a constant voltage 2.0v with 5.0ma driving ability with a capacitor connected. the GPCE040A has two 10-bit d/a with 2.0ma or 3.0ma driving current for audio outputs, dac1 and dac2.
GPCE040A ? generalplus technology inc. proprietary & confidential 11 oct 01, 2013 version: 1.4 6.11. serial interface i/o (sio) serial interface i/o offers a one-bit serial interface for communication. this serial interf ace is capable of transmitting or receiving data via two i/o pins, iob0 (sck) and iob1 (sda). ax+1 ax ax-1 a0 dx+1 dx d0 dx+1 dx d0 sda 1st write p_sio_data (w), $701ah 2nd write p_sio_data (w), $701ah stop write mode ax+1 ax ax-1 a0 dx+1 dx d0 dx+1 dx d0 sck sda sda 1st read p_sio_data (r), $701ah 2nd read p_sio_data (r), $701ah stop read mode write control bit=0 read control bit = 1 sck sda 6.12. uart uart block provides a full-duplex standard interface that facilitates the communication with other devices. with this interface, gpce can transmit and receive simultaneously. the maximum baud-rate can be up to 115200bps. this function can be accomplished by using portb and interrupt (uart irq). the rx and tx of uart are shared with iob7 and iob10. when GPCE040A receives and/or transmits a frame of data, the b7 (rxrdy) and/or b6 (txrdy) in port_uart_command2(r) will be set to ?1? and the uart irq is activated at the same time. d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit 8-bit data can be enabled/disable; also even/odd check 1-bit stop 1-bit start 6.13. audio algorithm the following speech types can be used in GPCE040A: pcm, sacm_s200, sacm_s480, sacm_s530, sacm_s720, sacm_a1600, sacm_a1601, sacm_a3600, sacm_dvr520, sacm_dvr1600, sacm_dvr3200, and sacm_dvr4800. for melody synthesis, the GPCE040A supports sacm_ms01 (fm) and sacm_ms02 (wave-table) synthesizers. 6.14. bonding option summary the GPCE040A has the following bonding option: 6.14.1. watchdog function wdgopt is the optional pin for watchdog by bonding option. the shape looks as the figure given below. when watchdog is selected, wdgopt is unbonded. if watchdog is not selected, wdgopt is bonded. the reason for wdgopt adjacent to vdd is that when watchdog is not selected, it is easy to make the connection between vdd and wdgopt. vdd wdgopt
GPCE040A ? generalplus technology inc. proprietary & confidential 12 oct 01, 2013 version: 1.4 7. electrical specifications 7.1. absolute maximum ratings characteristics symbol ratings dc supply voltage v + < 4.0v porta/b pad supply voltage v io < 7.0v input voltage range v in -0.5v to v + + 0.5v operating temperature t a 0 to + 60 storage temperature t sto -50 to + 150 note: stresses beyond those given in the absolute maximum rating table may cause operational errors or damage to the device. for no rmal operational conditions see dc electrical characteristics. 7.2. dc characteristics (vdd = 3.3v, vdd io = 5.5v (porta & b), t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2.4 3.3 3.6 v - operating current i op - 26 - ma f osc = 49.152mhz, ad, dac disable, no loading standby current i stb - - 2.0 a disable 32khz crystal input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output high current i oh - -5.0 - ma v oh = 4.0v output low current i ol - 12 - ma v ol = 1.0v input pull-low resister (pa15 :0, pb15 :0) r pl - 110 - k v in = vdd io input pull-high resister (pa15 :0, pb15 :0) r ph - 150 - k v in = vss 7.3. dc characteristics (vdd = 3.3v, vdd io = 3.3v (porta & b), t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2.4 3.3 3.6 v - operating current i op - 26 - ma f osc = 49.152mhz, ad, dac disable, no loading standby current i stb - - 2.0 a disable 32khz crystal input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output high current i oh - -2.9 - ma v oh = 2.6v output low current i ol - 6.7 - ma v ol = 0.7v input pull-low resister (pa15 :0, pb15 :0) r pl - 175 - k v in = vdd io input pull-high resister (pa15 :0, pb15 :0) r ph - 242 - k v in = vss
GPCE040A ? generalplus technology inc. proprietary & confidential 13 oct 01, 2013 version: 1.4 7.4. dc characteristics (vdd = 2.7v, vdd io = 2.7v (porta & b) , t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2.4 2.7 3.6 v - operating current i op - 17 - ma f osc = 49.152mhz, ad, dac disable, no loading standby current i stb - - 2.0 a disable 32khz crystal input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output high current i oh - -1.9 - ma v oh = 2.1v output low current i ol - 4.4 - ma v ol = 0.5v input pull-low resister (pa15 :0, pb15 :0) r pl - 230 - k v in = vdd io input pull-high resister (pa15 :0, pb15 :0) r ph - 325 - k v in = vss 7.5. dc characteristics (vdd = 2.4v, vdd io = 2.4v (porta & b) ,t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2.4 2.4 3.6 v - operating current i op - 14 - ma f osc = 49.152mhz, ad, dac disable, no loading standby current i stb - - 2.0 a disable 32khz crystal input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output high current i oh - -1.5 - ma v oh = 1.92v output low current i ol - 3.5 - ma v ol = 0.48v input pull-low resister (pa15 :0, pb15 :0) r pl - 275 - k v in = vdd io input pull-high resister (pa15 :0, pb15 :0) r ph - 395 - k v in = vss
GPCE040A ? generalplus technology inc. proprietary & confidential 14 oct 01, 2013 version: 1.4 7.6. adc characteristics (vdd = 3.3v, t a = 25 ) unit characteristics symbol min. typ. max. unit adc power dissipation for line_in iadc - 1.0 - ma adc power dissipation for mic_in - - 1.9 - ma adc line_in input voltage range from ioa[6:0] vinl (note 1) vss-0.3 - vdd+0.3 v adc microphone input voltage range vinm vss-0.3 - vdd+0.3 v external adc top voltage vextref (note 2) 2.0 - vdd+0.3 v resolution of adc reso - - 10 bits signal-to-noise plus distortion of adc from line in sinad (note 4) - 56 - db effective number of bit enob (note 5) 8.0 9.0 - bits integral non-linearity of adc inl - 4.0 - lsb (note 3) differential non-linearity of adc dnl (note 6) - 0.5 - lsb ad conversion rate f conv - - fcpu/512 hz microphone amplifier gain (note 7) a mic - - 42 db note1: internal protection diodes clamp the analog input to vdd and vss. these diodes allow the analog input to swing from (vss-0.3v) to (vdd+0.3v) without causing damages to the devices. note2: the adc performance is limited by the system noise level and therefore, the GPCE040A only guarantees to the 8-bit accuracy whe n vextref is 2.0v. note3: the lsb means least significant bit. vinl = 2.0v, 1lsb = 2.0v/2^10 = 1.953mv. note4: the sinad testing condition at vinlp-p = 0.8*vdd, f conv = fcpu/512 = 49mhz/512 = 95khz, fin=1.0khz sine waves at vdd = 3.0v from the ioa [6:0] input. note5: enob = (sinad-1.76)/6.02. note6: the adc of GPCE040A guarantees no data missed during conversion. note7: the microphone amplifier maximum gain = 15 * (60k/(1.5k+rext) v/v. the rext is external resistor between opi and micout. the g ain is 132v/v (=42db) when rext is 5.1k. 7.7. dac characteristics (t a = 25 ) unit characteristics test condition symbol min. typ. max. unit dac resolution vdd = 3.3v reso - - 10 bit signal to noise ratio of dac vdd = 3.3v snr - 54 - db sample rate vdd = 3.3v f s - - 100k hz vdd = 3.3v (2.0ma mode) - 2.0 - output dac current (aud1, aud2) vdd = 3.3v (3.0ma mode) i aud - 3.0 - ma
GPCE040A ? generalplus technology inc. proprietary & confidential 15 oct 01, 2013 version: 1.4 7.8. pull high resister and vdd io 0 100 200 300 400 500 2.4 3.4 4.4 vdd io (v) r ph (kohms) 7.9. i/o output high current i oh and v oh 0 5 10 15 0.5 1.5 2.5 3.5 4.5 v oh (v) i oh (ma) 7.10. pull low resister and vdd io 2.4 3.4 4.4 vdd io (v) r pl (kohms) 0 100 200 300 7.11. i/o output low current i ol and v ol 0.5 1.5 2.5 3.5 4.5 v ol (v) i ol (ma) 0 10 20
GPCE040A ? generalplus technology inc. proprietary & confidential 16 oct 01, 2013 version: 1.4 8. application circuits 8.1. application circuit - (1) note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 17 oct 01, 2013 version: 1.4 8.2. application circuit - (2) GPCE040A vmic micp mic 3k 3k 1k micn 220 0.22 0.1 reset reset vddh(3.3v) dac1 0.1 1k 1k 0.22 6 0.1 100 gpy0030a 4 5 3 2 1 87 vddh(3.3v) dac2 0.1 1k 1k 0.22 6 0.1 100 gpy0030a 4 5 3 2 1 87 ioa[6:0] ioa[6:0] ioa[15:7] ioa[15:7] iob[15:0] iob[15:0] vddh(3.3v) 100 0.1 vddio vssio avdd (3.3v) 100 0.1 avdd avss vdd (3.3v) 100 0.1 vdd vss vcoin 3300p 3.3k 0.1 GPCE040A application circuit (mic_in and with gpy0030a audio amplifier, for 2-battery use only) 0.1 0.1 vdd 4.7k speaker1 speaker2 x32o x32i 32768hz micout opi 0.22 5.1k agc vadref 0.1 vextref v2vref 47 4.7 470k 0.22 5000p 20-50pf* 20-50pf* note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 18 oct 01, 2013 version: 1.4 8.3. application circuit - (3) GPCE040A ioa[6:0] ioa[6:0] ioa[15:7] ioa[15:7] iob[15:0] iob[15:0] vddh(5v) 100 0.1 vddio vssio avdd (3.3v) 100 0.1 avdd avss vdd (3.3v) 100 0.1 vdd vss GPCE040A application circuit (mic_in and with bjt amplifier, for 3-battery use only) gpy0029a vddh(5v) 2 1 3 0.1 reset reset dac1 dac2 vdd speaker1 vddh(5v) 0.1 200~2k speaker2 vddh(5v) 0.1 200~2k 4.7k vmic micp mic 3k 3k 1k 0.22 micn micout 220 opi 0.22 5.1k 0.22 vcoin 3300p 3.3k 0.1 x32o x32i 32768hz agc vadref 47 vextref v2vref 0.1 470k 4.7 5000p 20-50pf* 20-50pf* note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 19 oct 01, 2013 version: 1.4 8.4. application circuit - (4) GPCE040A 220 agc vadref 47 vextref v2vref ioa[6:0] ioa[6:0] ioa[15:7] ioa[15:7] iob[15:0] iob[15:0] vddh(3.3v) 100 0.1 vddio vssio avdd (3.3v) 100 0.1 avdd avss vdd (3.3v) 100 0.1 vdd vss GPCE040A application circuit (mic_in and with bjt amplifier, for 2-battery use only) 0.1 470k 4.7 0.1 reset reset dac1 dac2 vdd speaker1 vddh(3.3v) 0.1 200~2k speaker2 vddh(3.3v) 0.1 200~2k 4.7k vmic micp mic 3k 3k 1k micn micout opi 0.22 5.1k 0.22 vcoin 3300p 3.3k 0.1 x32o x32i 32768hz 5000p 0.22 20-50pf* 20-50pf* note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 20 oct 01, 2013 version: 1.4 8.5. application circuit - (5) note GPCE040A micp micn micout opi agc vadref 0.1 vextref v2vref ioa[6:0] ioa[6:0] vddh(5v) 100 0.1 vddio vssio avdd (3.3v) 100 0.1 avdd avss vdd (3.3v) 100 0.1 vdd vss GPCE040A application circuit (line_in and wi th bjt amplifier, for 3-battery use only) vmic (7-channel line_in) ioa[15:7] ioa[15:7] iob[15:0] iob[15:0] vcoin 3300p 3.3k 0.1 0.1 reset reset vdd dac1 dac2 speaker1 0.1 200~2k speaker2 vddh(3.3v) 0.1 200~2k vddh(3.3v) 4.7k x32o x32i 20-50pf* 32768hz note: case(1): use avdd(internal) as ad top reference voltage by setting p_adc_ctrl($7015) b7 = 0 vextref v2vref case(2): use v2vref as ad top reference voltage by setting p_adc_ctrl($7015) b7 = 1, b8 = 0 0.1 f 100 f case(3): use external signal as ad top reference voltage by setting p_adc_ctrl($7015) b7 =1, b8 = 1. (detail see the programming guide) vextref v2vref vextref v2vref input external signal as ad top reference voltage. gpy0029a vddh(5v) 2 1 3 20-50pf* note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 21 oct 01, 2013 version: 1.4 8.6. application circuit - (6) GPCE040A application circuit (line_in and with bjt amplifier, for 2-battery use only) note GPCE040A micp micn micout opi agc vadref 0.1 vextref v2vref ioa[6:0] ioa[6:0] vddh(3.3v) 100 0.1 vddio vssio avdd (3.3v) 100 0.1 avdd avss vdd (3.3v) 100 0.1 vdd vss vmic (7-channel line_in) ioa[15:7] ioa[15:7] iob[15:0] iob[15:0] vcoin 3300p 3.3k 0.1 0.1 reset reset vdd dac1 dac2 speaker1 0.1 200~2k speaker2 vddh(3.3v) 0.1 200~2k vddh(3.3v) 4.7k x32o x32i 20-50pf* 32768hz note: case(1): use avdd(internal) as ad top reference voltage by setting p_adc_ctrl($7015) b7 = 0 vextref v2vref case(2): use v2vref as ad top reference voltage by setting p_adc_ctrl($7015) b7 = 1, b8 = 0 0.1 f100 f case(3): use external signal as ad top reference voltage by setting p_adc_ctrl($7015) b7 =1, b8 = 1. (detail see the programming guide) vextref v2vref vextref v2vref input external signal as ad top reference voltage. 20-50pf* note*: these capacitor values are for design guidance only. different capacitor values may be required for different crystal/resonat or used.
GPCE040A ? generalplus technology inc. proprietary & confidential 22 oct 01, 2013 version: 1.4 9. package/pad locations 9.1. ordering information product number package type GPCE040A-nnnv-c chip form GPCE040A-nnnv-hl04n-w green package form - lqfp 80 note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). note3: hl04n-w, hl04 is assign for lqfp80, n is assign for customer , w is watch dog bonding option (w=0 enable, w=1 disable). 9.2. package information 9.2.1. lqfp 80 c l1 e1 e e b d d1 a a2 a1 dimension in inch symbol min. typ. max. a - - 0.063 a1 0.002 - 0.006 a2 0.053 0.055 0.057 b 0.007 0.009 0.011 c 0.004 - 0.008 d 0.551 bsc. d1 0.472 bsc.
GPCE040A ? generalplus technology inc. proprietary & confidential 23 oct 01, 2013 version: 1.4 dimension in inch symbol min. typ. max. e 0.551 bsc. e1 0.472 bsc. e 0.020 bsc. l1 0.039 ref pad no. pad name pad no. pad name 1 x32o 38 vddio 2 x32i 39 vddio 3 test 40 ioa8 4 n/c 41 n/c 5 vdd 42 n/c 6 n/c 43 ioa9 7 n/c 44 ioa10 8 vss 45 ioa11 9 n/c 46 ioa12 10 vss 47 ioa13 11 n/c 48 ioa14 12 dac1 49 ioa15 13 dac2 50 n/c 14 v2vref 51 n/c 15 avss 52 vssio 16 agc 53 n/c 17 opi 54 sleep 18 micout 55 iob15 19 micn 56 iob14 20 n/c 57 iob13 21 micp 58 iob12 22 vadref 59 iob11 23 vextref 60 nc 24 avdd 61 n/c 25 vmic 62 n/c 26 n/c 63 in/c 27 vss 64 vddio 28 ioa0 65 iob10 29 ioa1 66 iob9 30 ioa2 67 iob8 31 ioa3 68 iob7 32 ioa4 69 iob6 33 ioa5 70 iob5 34 ioa6 71 iob4 35 ioa7 72 iob3 36 vssio 73 iob2 37 vssio 74 iob1
GPCE040A ? generalplus technology inc. proprietary & confidential 24 oct 01, 2013 version: 1.4 pad no. pad name pad no. pad name 75 iob0 78 vdd 76 reset 79 vcoin 77 n/c 80 vss
GPCE040A ? generalplus technology inc. proprietary & confidential 25 oct 01, 2013 version: 1.4 10. disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringement. further, generalplus makes no warranty of merchantability or fitness for any purpose. generalplus reserves the right to halt production or alter the specifications and prices at any time without notice. acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal co mmercial applications. applications invo lving unusual environmental or reli ability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional processing by generalplus for such applications. please note th at application circuits illustrated in this document are for reference purposes only.
GPCE040A ? generalplus technology inc. proprietary & confidential 26 oct 01, 2013 version: 1.4 11. revision history date revision # description page oct. 01, 2013 1.4 add comair logo to the cover page oct. 12, 2010 1.3 modify 3. features 4 may 23, 2008 1.2 modify 8. application circuits. 16-21 jul. 04,2006 1.1 1. modify the 9.2 ordering information. 2. delete the 9.3.2 plcc84. 3. modify the 8. application circuits. 21 24 15-20 dec. 14, 2005 1.0 original note: the GPCE040A data sheet v1.0 is a continued version of spce040a data sheet v0.4. 27

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